/* * Copyright 2024 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */ #ifndef _thm_14_0_2_OFFSET_HEADER #define _thm_14_0_2_OFFSET_HEADER // addressBlock: thm_thm_SmuThmDec // base address: 0x59800 #define regTHM_TCON_CUR_TMP 0x0000 #define regTHM_TCON_CUR_TMP_BASE_IDX 0 #define regTHM_TCON_HTC 0x0001 #define regTHM_TCON_HTC_BASE_IDX 0 #define regTHM_TCON_THERM_TRIP 0x0002 #define regTHM_TCON_THERM_TRIP_BASE_IDX 0 #define regTHM_CTF_DELAY 0x0003 #define regTHM_CTF_DELAY_BASE_IDX 0 #define regTHM_GPIO_PROCHOT_CTRL 0x0004 #define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 #define regTHM_GPIO_THERMTRIP_CTRL 0x0005 #define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 #define regTHM_GPIO_PWM_CTRL 0x0006 #define regTHM_GPIO_PWM_CTRL_BASE_IDX 0 #define regTHM_GPIO_TACHIN_CTRL 0x0007 #define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 #define regTHM_GPIO_PUMPOUT_CTRL 0x0008 #define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 #define regTHM_GPIO_PUMPIN_CTRL 0x0009 #define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 #define regTHM_THERMAL_INT_ENA 0x000a #define regTHM_THERMAL_INT_ENA_BASE_IDX 0 #define regTHM_THERMAL_INT_CTRL 0x000b #define regTHM_THERMAL_INT_CTRL_BASE_IDX 0 #define regTHM_THERMAL_INT_STATUS 0x000c #define regTHM_THERMAL_INT_STATUS_BASE_IDX 0 #define regTHM_SW_TEMP 0x000d #define regTHM_SW_TEMP_BASE_IDX 0 #define regCG_MULT_THERMAL_CTRL 0x000e #define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 #define regCG_MULT_THERMAL_STATUS 0x000f #define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 #define regCG_THERMAL_RANGE 0x0010 #define regCG_THERMAL_RANGE_BASE_IDX 0 #define regCG_FDO_CTRL0 0x0011 #define regCG_FDO_CTRL0_BASE_IDX 0 #define regCG_FDO_CTRL1 0x0012 #define regCG_FDO_CTRL1_BASE_IDX 0 #define regCG_FDO_CTRL2 0x0013 #define regCG_FDO_CTRL2_BASE_IDX 0 #define regCG_TACH_CTRL 0x0014 #define regCG_TACH_CTRL_BASE_IDX 0 #define regCG_TACH_STATUS 0x0015 #define regCG_TACH_STATUS_BASE_IDX 0 #define regCG_THERMAL_STATUS 0x0016 #define regCG_THERMAL_STATUS_BASE_IDX 0 #define regCG_PUMP_CTRL0 0x0017 #define regCG_PUMP_CTRL0_BASE_IDX 0 #define regCG_PUMP_CTRL1 0x0018 #define regCG_PUMP_CTRL1_BASE_IDX 0 #define regCG_PUMP_CTRL2 0x0019 #define regCG_PUMP_CTRL2_BASE_IDX 0 #define regCG_PUMP_TACH_CTRL 0x001a #define regCG_PUMP_TACH_CTRL_BASE_IDX 0 #define regCG_PUMP_TACH_STATUS 0x001b #define regCG_PUMP_TACH_STATUS_BASE_IDX 0 #define regCG_PUMP_STATUS 0x001c #define regCG_PUMP_STATUS_BASE_IDX 0 #define regTHM_TCON_LOCAL2 0x001d #define regTHM_TCON_LOCAL2_BASE_IDX 0 #define regTHM_TCON_LOCAL3 0x001e #define regTHM_TCON_LOCAL3_BASE_IDX 0 #define regTHM_TCON_LOCAL4 0x001f #define regTHM_TCON_LOCAL4_BASE_IDX 0 #define regTHM_TCON_LOCAL5 0x0020 #define regTHM_TCON_LOCAL5_BASE_IDX 0 #define regTHM_TCON_LOCAL6 0x0021 #define regTHM_TCON_LOCAL6_BASE_IDX 0 #define regTHM_TCON_LOCAL7 0x0022 #define regTHM_TCON_LOCAL7_BASE_IDX 0 #define regTHM_TCON_LOCAL8 0x0023 #define regTHM_TCON_LOCAL8_BASE_IDX 0 #define regTHM_TCON_LOCAL9 0x0024 #define regTHM_TCON_LOCAL9_BASE_IDX 0 #define regTHM_TCON_LOCAL10 0x0025 #define regTHM_TCON_LOCAL10_BASE_IDX 0 #define regTHM_TCON_LOCAL11 0x0026 #define regTHM_TCON_LOCAL11_BASE_IDX 0 #define regTHM_TCON_LOCAL12 0x0027 #define regTHM_TCON_LOCAL12_BASE_IDX 0 #define regTHM_TCON_LOCAL13 0x0028 #define regTHM_TCON_LOCAL13_BASE_IDX 0 #define regTHM_TCON_LOCAL14 0x0029 #define regTHM_TCON_LOCAL14_BASE_IDX 0 #define regTHM_TCON_LOCAL15 0x002a #define regTHM_TCON_LOCAL15_BASE_IDX 0 #define regTHM_BACO_CNTL 0x002d #define regTHM_BACO_CNTL_BASE_IDX 0 #define regTHM_BACO_TIMING0 0x002e #define regTHM_BACO_TIMING0_BASE_IDX 0 #define regTHM_BACO_TIMING1 0x002f #define regTHM_BACO_TIMING1_BASE_IDX 0 #define regTHM_BACO_TIMING2 0x0030 #define regTHM_BACO_TIMING2_BASE_IDX 0 #define regTHM_BACO_TIMING 0x0031 #define regTHM_BACO_TIMING_BASE_IDX 0 #define regXTAL_CNTL 0x0032 #define regXTAL_CNTL_BASE_IDX 0 #define regTHM_PWRMGT 0x0033 #define regTHM_PWRMGT_BASE_IDX 0 #define regSMUSBI_SBIREGADDR 0x0158 #define regSMUSBI_SBIREGADDR_BASE_IDX 0 #define regSMUSBI_SBIREGDATA 0x0159 #define regSMUSBI_SBIREGDATA_BASE_IDX 0 #define regSMUSBI_ERRATA_STAT_REG 0x015d #define regSMUSBI_ERRATA_STAT_REG_BASE_IDX 0 #define regSMUSBI_SBICTRL 0x015e #define regSMUSBI_SBICTRL_BASE_IDX 0 #define regSMUSBI_CKNBIRESET 0x015f #define regSMUSBI_CKNBIRESET_BASE_IDX 0 #define regSMUSBI_TIMING 0x0160 #define regSMUSBI_TIMING_BASE_IDX 0 #define regSMUSBI_HS_TIMING 0x0161 #define regSMUSBI_HS_TIMING_BASE_IDX 0 #define regSBTSI_REMOTE_TEMP 0x0162 #define regSBTSI_REMOTE_TEMP_BASE_IDX 0 #define regSBRMI_CONTROL 0x0163 #define regSBRMI_CONTROL_BASE_IDX 0 #define regSBRMI_COMMAND 0x0164 #define regSBRMI_COMMAND_BASE_IDX 0 #define regSBRMI_WRITE_DATA0 0x0166 #define regSBRMI_WRITE_DATA0_BASE_IDX 0 #define regSBRMI_WRITE_DATA1 0x0167 #define regSBRMI_WRITE_DATA1_BASE_IDX 0 #define regSBRMI_WRITE_DATA2 0x0168 #define regSBRMI_WRITE_DATA2_BASE_IDX 0 #define regSBRMI_READ_DATA0 0x016a #define regSBRMI_READ_DATA0_BASE_IDX 0 #define regSBRMI_READ_DATA1 0x016b #define regSBRMI_READ_DATA1_BASE_IDX 0 #define regSBRMI_CORE_EN_NUMBER 0x016c #define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 #define regSBRMI_CORE_EN_STATUS0 0x016d #define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 #define regSBRMI_CORE_EN_STATUS1 0x016e #define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 #define regSBRMI_APIC_STATUS0 0x016f #define regSBRMI_APIC_STATUS0_BASE_IDX 0 #define regSBRMI_APIC_STATUS1 0x0170 #define regSBRMI_APIC_STATUS1_BASE_IDX 0 #define regSBRMI_MCE_STATUS0 0x0171 #define regSBRMI_MCE_STATUS0_BASE_IDX 0 #define regSBRMI_MCE_STATUS1 0x0172 #define regSBRMI_MCE_STATUS1_BASE_IDX 0 #define regSMBUS_CNTL0 0x0173 #define regSMBUS_CNTL0_BASE_IDX 0 #define regSMBUS_CNTL1 0x0174 #define regSMBUS_CNTL1_BASE_IDX 0 #define regSMBUS_BLKWR_CMD_CTRL0 0x0175 #define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 #define regSMBUS_BLKWR_CMD_CTRL1 0x0176 #define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 #define regSMBUS_BLKRD_CMD_CTRL0 0x0177 #define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 #define regSMBUS_BLKRD_CMD_CTRL1 0x0178 #define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 #define regSMBUS_TIMING_CNTL0 0x0179 #define regSMBUS_TIMING_CNTL0_BASE_IDX 0 #define regSMBUS_TIMING_CNTL1 0x017a #define regSMBUS_TIMING_CNTL1_BASE_IDX 0 #define regSMBUS_TIMING_CNTL2 0x017b #define regSMBUS_TIMING_CNTL2_BASE_IDX 0 #define regSMBUS_TRIGGER_CNTL 0x017c #define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 #define regSMBUS_UDID_CNTL0 0x017d #define regSMBUS_UDID_CNTL0_BASE_IDX 0 #define regSMBUS_UDID_CNTL1 0x017e #define regSMBUS_UDID_CNTL1_BASE_IDX 0 #define regSMBUS_UDID_CNTL2 0x017f #define regSMBUS_UDID_CNTL2_BASE_IDX 0 #define regSMUSBI_SMBUS 0x0180 #define regSMUSBI_SMBUS_BASE_IDX 0 #define regSMUSBI_ALERT 0x0181 #define regSMUSBI_ALERT_BASE_IDX 0 #define regSMBUS_BACO_DUMMY 0x0182 #define regSMBUS_BACO_DUMMY_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE0_LOW 0x0183 #define regSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE0_HIGH 0x0184 #define regSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE1_LOW 0x0185 #define regSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE1_HIGH 0x0186 #define regSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE2_LOW 0x0187 #define regSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE2_HIGH 0x0188 #define regSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE3_LOW 0x0189 #define regSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE3_HIGH 0x018a #define regSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE4_LOW 0x018b #define regSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX 0 #define regSMBUS_BACO_ADDR_RANGE4_HIGH 0x018c #define regSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX 0 #endif